US 2014/0181604 A1 · CHANNEL CONTROL CIRCUIT AND SEMICONDUCTOR DEVICE HAVING THE SAME

Abstract

A channel control circuit having a plurality of channels according to an embodiment of the present invention includes: a channel control signal generating block configured to generate a channel control signal capable of selectively controlling an activated state of a channel in response to a combination of a first test mode signal and a second test mode signal; a scan buffer control signal generating block configured to generate a scan buffer control signal in response to the first test mode signal and a scan signal; a clock buffer control signal generating block configured to generate a clock buffer control signal in response to the channel control signal and the scan buffer control signal; and a clock input buffer configured to generate a clock output signal, which is used as an internal clock of a semiconductor device, in response to the clock buffer control signal.

Claims17

Dependent claims

A channel control circuit having a plurality of channels, comprising:

a channel control signal generating block configured to generate a channel control signal capable of selectively controlling an activated state of a channel in response to a combination of a first test mode signal and a second test mode signal;
a scan buffer control signal generating block configured to generate a scan buffer control signal in response to the first test mode signal and a scan signal;
a clock buffer control signal generating block configured to generate a clock buffer control signal in response to the channel control signal and the scan buffer control signal;
and
a clock input buffer configured to generate a clock output signal in response to the clock buffer control signal, wherein the clock output signal is used as an internal clock of a semiconductor device.

2 more elements

A semiconductor device, comprising:

a first channel comprising a first channel control circuit;
and
is a second channel comprising a second channel control circuit, wherein the first channel control circuit is configured to apply a clock signal for a test operation to the first channel when the second channel control circuit does not apply a clock signal for a test operation to the second channel in a Direct Access mode for simultaneously testing the first and second channels of the semiconductor memory.

Dependencies are inferred from the claim text.

Channel control circuit and semiconductor device having the same

Life of this patent

Channel control circuit and semiconductor device having the same

Life of this patent

Abstract

Claims17