Method and apparatus for tuning scan capture phase activity factor

An integrated circuit comprising:

• a plurality of logic circuits, the logic circuits grouped into clock regions;
• a plurality of clocks to drive the logic circuits of each clock region;
• a plurality of control gates, each control gate being coupled to one of the plurality of clocks, the control gates to alternately enable and disable a respective clock to which it is coupled;
• and
• a scan chain coupled to each control gate to receive vectors through a scan input to set the state of each control gate.

A machine-readable medium having instructions thereon that when executed by the machine cause the machine to perform operations comprising:

• determining an activity factor for normal operation of a die to be tested;
• loading a sequence of scan vectors into the die for a structural scan test;
• disabling clock regions of the die to lower the activity factor of the structural scan test by an amount based on the determined activity factor;
• running the structural scan test in a capture phase with the disabled clock regions;
• and
• receiving test results from the die based on the structural scan test.