Modeling memory arrays for test pattern analysis
AssigneeAdvanced Micro Devices, Inc.
InventorsVibhor Mittal, Anirudh Kadiyala
Life of this patent
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Abstract
A method includes receiving in a computing apparatus a model of an integrated circuit device including a memory array. The memory array is modeled as a plurality of device primitives. A test pattern analysis of the memory array is performed using the model in the computing apparatus. A system includes a memory array modeling unit and a test pattern analysis unit. The memory array modeling unit is operable to generate a model of an integrated circuit device including an memory array. The memory array is modeled as a plurality of device primitives. The test pattern analysis unit is operable to performing a test pattern analysis of the memory array using the model in the computing apparatus.
Claims22
A method, comprising:
- receiving in a computing apparatus first and second models of an integrated circuit device including a memory array, wherein the memory array is modeled as a first plurality of device primitives in the first model and as a second plurality of device primitives in the second model, the second plurality of device primitives being different than the first plurality of device primitives;
- performing a test pattern analysis of the memory array using the first model in the computing apparatus to generate a plurality of test patterns for testing the memory array based on the first plurality of device primitives;
- and
- performing a fault grading analysis of the memory array using the second model and the plurality of test patterns in the computing device to determine fault coverage for the second model.
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A system, comprising:
- a memory array modeling unit to generate a first and second models of an integrated circuit device including a memory array, wherein the memory array is modeled as a first plurality of device primitives in the first model and as a second plurality of device primitives in the second model, the second plurality of device primitives being different than the first plurality of device primitives;
- an automated test pattern generation unit to perform a test pattern analysis of the memory array using the model to generate a plurality of test patterns for testing the memory array based on the first plurality of device primitives;
- and
- a fault grading unit to perform a fault grading analysis of the memory array using the second model and the plurality of test patterns to determine fault coverage for the second model.
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A non-transitory program storage device programmed with instructions, that, when executed by a computing apparatus, perform a method comprising:
- receiving first and second models of an integrated circuit device including a memory array, wherein the memory array is modeled as a first plurality of device primitives in the first model and as a second plurality of device primitives in the second model, the second plurality of device primitives being different than the first plurality of device primitives;
- performing a test pattern analysis of the memory array using the first model to generate a plurality of test patterns for testing the memory array based on the first plurality of device primitives;
- and
- performing a fault grading analysis of the memory array using the second model and the plurality of test patterns in the computing device to determine fault coverage for the second model.
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Dependencies are inferred from the claim text.