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US 2014/0181588 A1Published application
Semiconductor memory apparatus and operating method thereof
AssigneeSK hynix Inc.
InventorChan Gi GIL
Life of this patent
Estimating the term…
Abstract
A semiconductor memory apparatus includes: a user setting unit configured to generate test data and a delay control signal in response to an external command and an external address; a delay locked loop (DLL) clock generation unit including a replica configured to have a delay time controlled in response to the delay control signal; and a data output unit configured to output the test data in response to a DLL clock signal outputted from the DLL clock generation unit.
Claims10
A semiconductor memory apparatus comprising:
- a user setting unit configured to generate test data and a delay control signal in response to an external command and an external address;
- a delay locked loop (DLL) clock generation unit comprising a replica configured to have a delay time controlled in response to the delay control signal;
- and
- a data output unit configured to output the test data in response to a DLL clock signal provided from the DLL clock generation unit.
1 more element
An operating method of a semiconductor memory apparatus, comprising the steps of:
- inputting an external command so that the semiconductor memory apparatus enters a register setting mode;
- storing test data and a delay control signal in a setting register by inputting an external command;
- controlling the phase of a DLL clock signal by controlling a delay time of a replica according to the delay control signal;
- and
- outputting the test data in response to the DLL clock signal, and comparing the phases of the test data and an external clock signal.
2 more elements
A delay locked loop (DLL), comprising:
- a delay unit configured to delay an external clock signal by a set delay time, to generate the DLL clock signal;
- a phase comparison unit configured to generate a comparison signal by comparing the external clock signal and a feedback clock signal based on the DLL clock signal;
- and
- a replica configured to control a delay time of the DLL clock signal provided from an output terminal of the delay unit in response to a delay control signal, to generate the feedback clock,
- wherein the delay control signal is generated in response to an external command and an external address.
2 more elements
Dependencies are inferred from the claim text.