Speculative non-faulting loads and gathers
AssigneeIntel Corporation
InventorsJayashankar BHARADWAJ, Nalini VASUDEVAN, Victor W. LEE, Sara S. BAGHSORKHI, Albert HARTONO, Daehyun KIM
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AssigneeIntel Corporation
InventorsJayashankar BHARADWAJ, Nalini VASUDEVAN, Victor W. LEE, Sara S. BAGHSORKHI, Albert HARTONO, Daehyun KIM
Estimating the term…
According to one embodiment, a processor includes an instruction decoder to decode an instruction to read a plurality of data elements from memory, the instruction having a first operand specifying a storage location, a second operand specifying a bitmask having one or more bits, each bit corresponding to one of the data elements, and a third operand specifying a memory address storing a plurality of data elements. The processor further includes an execution unit coupled to the instruction decoder, in response to the instruction, to read one or more data elements speculatively, based on the bitmask specified by the second operand, from a memory location based on the memory address indicated by the third operand, and to store the one or more data elements in the storage location indicated by the first operand.
A processor, comprising:
A method, comprising:
A system comprising:
Dependencies are inferred from the claim text.