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US 2014/0181574 A1Published application
Error correction and recovery in chained memory architectures
AssigneeMicron Technology, Inc.
InventorDavid R. Resnick
Life of this patent
Estimating the term…
Abstract
Electronic apparatus, systems, and methods to construct and operate the electronic apparatus and/or systems include a memory unit configured to receive data flow from two directions. The memory unit can be configured serially in a chain with other memory units. The chain can include an error check and correcting unit (ECC). Additional apparatus, systems, and methods are disclosed.
Claims26
A memory unit comprising:
- a memory section having a plurality of memory devices arranged as a stack of individual memory chips;
- and
- an interface section coupled to the memory section, the interface section structured to couple into a chain exterior to the memory unit, and further structured to allow access to the memory section in response to a request to access the memory section received from either of two directions in the chain.
An apparatus comprising:
- a plurality of memory units, the memory units configured serially in a chain, each memory unit including:
- a memory section having a plurality of memory devices arranged as stack of individual memory chips;
- and
- a logic chip coupled to the memory section, the logic chip structured to couple into the chain and further structured to allow access to the memory section in response to a request to access the memory section received from either of two directions in the chain;
- and
- an error check and correcting (ECC) unit serially coupled in the chain, the ECC unit being an individual unit in the chain separate from the memory units, the chain being separate from and connectable to a controller, the controller operable to control flow of data along the chain.
3 more elements
A method comprising:
- operating on information flow in a plurality of memory units, the memory units configured serially in a chain, each memory unit having a plurality of memory devices arranged as a stack of individual memory chips and having a logic chip coupled to the stack, the logic chip structured to couple into the chain and further structured to allow access to the respective memory unit in response to a request to access the respective memory unit received from either of two directions in the chain;
- and
- performing error recovery in the chain following a determination of an error in the chain.
Dependencies are inferred from the claim text.