Signal processing circuitry with frontend and backend circuitry controlled by separate clocks

A method comprising the steps of:

• determining an equalized read channel signal from a read channel signal;
• performing an iterative decoding process on the equalized read channel signal to determine a decoded read channel signal;
• applying verification and scrambling processing on the decoded read channel signal;
• wherein the determining and applying steps are controlled by a first clock having an associated first clock rate and wherein the performing step is controlled by a second clock having an associated second clock rate, the second clock rate being determined at least in part by the first clock rate and a maximum clock rate.

A storage device comprising:

• at least one storage medium;
• a read head configured to read data from the storage medium;
• and
• control circuitry coupled to the read head and configured to process data received from the read head;
• the control circuitry comprising:
• read channel circuitry;
• and
• signal processing circuitry associated with the read channel circuitry, the signal processing circuitry comprising:
• frontend processing circuitry comprising a loop detector and equalizer configured to determine an equalized read channel signal from a read channel signal and a decoding module configured to apply verification and scrambling processing on a decoded read channel signal;
• backend processing circuitry comprising a backend detector, an interleaver, a backend decoder, and a de-interleaver, the backend processing circuitry being configured to perform an iterative decoding process on the equalized read channel signal to determine the decoded read channel signal;
• wherein the frontend processing circuitry is controlled by a first clock having an associated first clock rate and wherein the backend processing circuitry is controlled by a selected one of the first clock and a second clock having an associated second clock rate, the second clock rate being determined at least in part by the first clock rate and a maximum clock rate.