Interface for controlling the phase alignment of clock signals for a recipient device

A method of aligning clocks signals within interface circuitry for transmitting transactions from an initiator to a recipient, said interface circuitry comprising:

• receiving a clock signal;
• transmitting said clock signal to at least one clock output via a first path;
• transmitting said clock signal via a second path to at least one synchronising circuit for transmitting transactions to at least one transaction output in response to said clock signal and to a further synchronising circuit configured to have a similar delay to said at least one synchronising circuit;
• delaying said clock signal by a controllable delay circuit on one of said first or second paths;
• calibrating said controllable delay circuit by adjusting a delay of said controllable delay circuit and detecting a phase difference between a clock signal output by said further synchronising circuit and a clock signal from a location close to said at least one clock output, until alignment of said two clock signals is detected;
• and
• setting a delay of said controllable delay circuit to a value dependent upon said delay that caused said alignment detected during said calibrating step.

Interface means for transmitting transactions between an initiating means and a receiving means, said interface means comprising:

• a clock input means for receiving a clock signal;
• at least one transaction input means for receiving transactions;
• at least one clock output means for outputting said clock signal;
• a first clock path for transmitting said clock signal from said clock input to said clock output;
• at least one transaction output means for outputting said transactions to said recipient;
• at least one synchronising means clocked by said clock signal for transmitting said transactions to said at least one transaction output in response to said clock signal;
• a second clock path for transmitting said clock signal from said clock input to said at least one synchronising circuit;
• a controllable delay means arranged on one of said first or said second clock paths for providing said clock signal with a delay;
• a further synchronising means for providing a similar delay to said at least one synchronising means and arranged in parallel with said at least one synchronising means on said second clock path;
• phase detection means for receiving a clock signal output by said further synchronising means and a clock signal from said first clock path close to said at least one clock output and for detecting alignment of said received clock signals;
• and
• calibration control means for adjusting a delay of said controllable delay circuit during calibration until said phase detection means detects said alignment of said clock signals;
• said calibration control mean being for controlling said controllable delay circuit to generate a delay to said clock signal in dependence upon said delay that generated said alignment detected during calibration during operation of said interface means.