US 2014/0181560 A1 · PLATFORM POWER CONSUMPTION REDUCTION VIA POWER STATE SWITCHING

Abstract

Methods and apparatus relating to platform power consumption reduction via power state switching are described. In one embodiment, control logic causes a processor to enter a first low power consumption state (e.g., S0ix) instead of a second low power consumption state (e.g., S3) based on whether a threshold time period exists between a first wake event (e.g., corresponding to a first one of one or more awake requests) and a second wake event (e.g., corresponding to a second one of the one or more awake requests). Other embodiments are also claimed and disclosed.

Claims25

Dependent claims

An apparatus comprising:

control logic, the control logic at least partially comprising hardware logic, to cause a processor to enter a first low power consumption state instead of a second low power consumption state based on a threshold time period between a first wake event and a second wake event,
wherein the first low power consumption state is to consume more power than the second low power consumption state.

Dependencies are inferred from the claim text.

Facts

Application

14/139,864Filed 23 Dec 2013

Priority

IN 5444/CHE/201226 Dec 2012

Published

26 Jun 2014

Term ends

Not estimatedThe source records don’t support an estimate.

Classification6 codes

G06F 1/3287
Power saving characterised by the action undertaken: by switching off individual functional units in the computer system
G06F 1/3265
Power saving in peripheral device: power saving in display device
G06F 1/3206
Power management, i.e. event-based initiation of a power-saving mode: monitoring of events, devices or parameters that trigger a change in power…
Y02D 10/00
Energy efficient computing

Platform power consumption reduction via power state switching

Life of this patent

Platform power consumption reduction via power state switching

Life of this patent

Abstract

Claims25