Methods and apparatus related to processor sleep states
AssigneeAdvanced Micro Devices, Inc.
InventorsAlexander J. Branover, Andrew W. Lueck, Paul E. Kitchin, David A. Kaplan
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Abstract
A system includes a processor including at least a first core and a local interrupt controller associated with the first core. The first core is operable to store its architectural state prior to entering a first core sleep state, and the processor is operable to receive and implement a request for entering a system sleep state in which the first core is in the first core sleep state and the local interrupt controller is powered down and exit the system sleep state by restoring the local interrupt controller and restoring the saved architectural state of the first core.
Claims20
A system, comprising:
- a processor comprising:
- at least a first core;
- and
- a local interrupt controller associated with the first core,
- wherein the first core is operable to store its architectural state prior to entering a first core sleep state, and
- wherein the processor is operable to receive and implement a request for entering a system sleep state in which the first core is in the first core sleep state and the local interrupt controller is powered down and exit the system sleep state by restoring the local interrupt controller and restoring the saved architectural state of the first core.
A method, comprising:
- storing the architectural state of a first core of a processor, the processor including a local interrupt controller associated with the first core;
- placing the first core into a first core sleep state;
- placing the processor into a system sleep state in which the first core is in the first core sleep state and the local interrupt controller is powered down;
- and
- exiting the system sleep state by restoring the local interrupt controller and restoring the saved architectural state of the first core.
A computer readable storage device encoded with data that, when implemented in a manufacturing facility, adapts the manufacturing facility to create a processor, comprising a processor including at least a first core coupled to the memory and a local interrupt controller associated with the first core, wherein the first core is operable to store its architectural state in the memory prior to entering a first core sleep state, and the processor is operable to receive and implement a request for placing the system into a system sleep state in which the first core is in the first core sleep state and the local interrupt controller is powered down and exit the system sleep state by restoring the local interrupt controller and restoring the saved architectural state of the first core.
Dependencies are inferred from the claim text.