Idle Phase Exit Prediction

An integrated circuit comprising:

• a functional unit configured to cycle between intervals of an active state and intervals of an idle state;
• and
• a power management unit configured to place the functional unit in a low power state responsive to the functional unit entering the idle state, and further configured to preemptively cause the functional unit to exit the low power state at a predetermined time after entering the low power state, wherein the predetermined time is based on a prediction of idle state duration made prior to entering the low power state.

A system comprising:

• a plurality of processor cores implemented on a system-on-a-chip (SoC), wherein each of the plurality of processor cores is configured to cycle between intervals of an active state and an idle state;
• and
• a power management unit configured to place a selected one of the processor cores into a low power state responsive to the selected one of the processor cores entering the idle state, and further configured to preemptively cause the selected one of the processor cores to exit the low power state at a predetermined time after entering the low power state, wherein the predetermined time is based on a prediction of idle state duration made prior to entering the low power state.

A computer readable storage medium comprising a data structure which is operated upon by a program executable on a computer system, the program operating on the data structure to perform a portion of a process to fabricate an integrated circuit including circuitry described by the data structure, the circuitry described in the data structure including:

• a functional unit configured to cycle between intervals of an active state and intervals of an idle state;
• and
• a power management unit configured to place the functional unit in a low power state responsive to the functional unit entering the idle state, and further configured to preemptively cause the functional unit to exit the low power state at a predetermined time after entering the low power state, wherein the predetermined time is based on a prediction of idle state duration made prior to entering the low power state.