Managing a power state of a processor
AssigneeIntel Corporation
InventorsDevadatta V. Bodas, Eric K. Mann
Life of this patent
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Abstract
A method and system for managing a power state of a processor are described herein. The method includes receiving, at the processor, a signal indicating that an interrupt is to be sent to the processor. The method also includes transitioning the processor from the deep idle state to the shallow idle state in response to receiving the signal and transitioning the processor from the shallow idle state to an active state in response to receiving the interrupt.
Claims34
A method for managing a power state of a processor, comprising:
- receiving, at a processor, a signal indicating that an interrupt is to be sent to the processor;
- in response to receiving the signal, transitioning the processor from a deep idle state to a shallow idle state;
- and
- transitioning the processor from the shallow idle state to an active state in response to receiving the interrupt.
A system for managing a power state of a processor, comprising:
- a processor that is configured to execute stored instructions;
- and
- a storage device that stores instructions, the storage device comprising processor executable code that, when executed by the processor, is configured to:
- receive a signal indicating that an interrupt is impending;
- transition the processor from a deep idle state to a shallow idle state in response to receiving the signal;
- and
- transition the processor from the shallow idle state to an active state in response to receiving the interrupt;
- and
- a device that is communicably coupled to the processor and is configured to:
- send the signal indicating that the interrupt is impending to the processor;
- and
- send the interrupt to the processor.
At least one machine readable medium having instructions stored therein that, in response to being executed on a processor, cause the processor to:
- receive a signal indicating that an interrupt is to be sent to the processor;
- in response to receiving the signal, transition the processor from a deep idle state to a shallow idle state;
- and
- transition the processor from the shallow idle state to an active state in response to receiving the interrupt.
A device for sending a signal indicating an impending interrupt to a processor, wherein the device is configured to:
- generate a signal indicating that an interrupt is to be sent to a processor of a system;
- determine a delay for sending the signal to the processor based on a delay for sending the interrupt to the processor;
- send the signal to the processor after the delay for sending the signal has elapsed;
- and
- send the interrupt to the processor after the delay for sending the interrupt has elapsed.
A method for sending a signal indicating an impending interrupt to a processor, comprising:
- generating a signal indicating that an interrupt is to be sent to a processor;
- determining a delay for sending the signal to the processor based on a delay for sending the interrupt to the processor, wherein the delay for sending the signal is less than the delay for sending the interrupt;
- sending the signal to the processor after the delay for sending the signal has elapsed;
- and
- sending the interrupt to the processor after the delay for sending the interrupt has elapsed.
Dependencies are inferred from the claim text.