Power control for multi-core data processor

A multi-core data processor comprising:

• a plurality of data processor cores, each data processor core comprising:
• a power state controller having a first input for receiving an idle signal, a second input, and an output for providing a current power state;
• and
• an idle timer having a first input for receiving said idle signal, a second input for receiving a release signal, and an output coupled to said second input of said power state controller, wherein said idle timer provides a value on said output indicating an elapsed time between an activation of said idle signal and an activation of said release signal;
• and
• wherein said power state controller transitions a corresponding data processor core from an active state to an idle state in response to said idle signal, and transitions said corresponding data processor core from said idle state to said active state after a time determined by said elapsed time and said corresponding data processor core operates in said active state thereafter in response to said release signal.

A method comprising:

• placing a data processor core of a plurality of data processor cores in an idle state;
• receiving a release signal;
• and
• determining whether to exit said idle state based on a condition of at least one other data processor core.

A method comprising:

• placing a data processor core in an idle state;
• receiving a release indication;
• and
• exiting said idle state selectively based on a length of time said data processor core was in said idle state.