Idle Phase Prediction For Integrated Circuits

An integrated circuit comprising:

• a functional unit configured to cycle between intervals of an active state and intervals of an idle state;
• and
• a prediction unit configured to record a history of idle state durations for the for a plurality of intervals of the idle state and further configured to predict a duration of the next interval of the idle state based on the history of idle state durations.

A system comprising:

• a plurality of processor cores implemented on a system-on-a-chip (SoC), wherein each of the plurality of processor cores is configured to cycle between intervals of an active state and an idle state;
• and
• a prediction unit implemented on the SoC and configured to, for each of the plurality of processor cores, record a corresponding history of idle state durations and further configured to predict a duration of the next interval of the idle state for each of the plurality of processor cores based on their respective histories of idle state durations.

A computer readable storage medium comprising a data structure which is operated upon by a program executable on a computer system, the program operating on the data structure to perform a portion of a process to fabricate an integrated circuit including circuitry described by the data structure, the circuitry described in the data structure including:

• a functional unit configured to cycle between intervals of an active state and intervals of an idle state;
• and
• a prediction unit configured to record a history of idle state durations for the for a plurality of intervals of the idle state and further configured to predict a duration of the next interval of the idle state based on the history of idle state durations.