Dynamic Balancing Of Power Across A Plurality Of Processor Domains According To Power Policy Control Bias
AssigneeIntel Corporation
InventorsJeremy J. Shrall, Jay D. Schwartz, Stephen H. Gunther
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Abstract
In an embodiment, a processor includes multiple domains including a core domain having at least one core to execute instructions and a graphics domain including at least one graphics engine to perform graphics operations and a power controller to control power consumption of the processor. The power controller may include a logic to receive an indication of a priority domain of the domains and to dynamically allocate power to the domains based on a power limit, one or more maximum domain frequency requests, and the priority domain indication. Other embodiments are described and claimed.
Claims22
A processor comprising:
- a plurality of domains including a core domain having at least one core to execute instructions;
- and
- a power controller to control power consumption of the processor, the power controller including a first logic to receive an indication of a priority domain of the plurality of domains and to dynamically allocate power to the plurality of domains based on a power limit, one or more maximum domain frequency requests, and the priority domain indication.
A machine-readable medium having stored thereon instructions, which if performed by a machine cause the machine to perform a method comprising:
- receiving a request to update a frequency of a first domain of a multi-domain processor;
- calculating a minimum power demand for a plurality of domains of the multi-domain processor and allocating the minimum power demand to each of the plurality of domains;
- determining if a portion of a power budget remains after the minimum power demand allocation;
- and
- if so, allocating at least part of the remaining power budget to a priority domain of the plurality of domains.
A system comprising:
- a multi-domain processor having a plurality of domains including a core domain having at least one core to execute instructions, the multi-domain processor further including a power allocation logic to receive a request to update a frequency of the core domain, calculate a minimum power demand for the plurality of domains and allocate a minimum power level to each of the plurality of domains, and allocate at least part of a remaining power budget to the core domain;
- and
- a dynamic random access memory (DRAM) coupled to the multi-domain processor.
Dependencies are inferred from the claim text.