Guardband reduction for multi-core data processor
AssigneeAdvanced Micro Devices, Inc.
InventorsSrilatha Manne, Rajagopalan Desikan, Sanjay Pant, Youngtaek Kim
Life of this patent
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Abstract
A multi-core data processor includes multiple data processor cores and a power controller. Each data processor core has a first input for receiving a clock signal, a second input for receiving a power supply voltage, and an output for providing an idle signal. The power controller is coupled to each of the data processor cores for providing the clock signal and the power supply voltage to each of the data processor cores. The power controller provides at least one of the clock signal and the power supply voltage to an active one of the data processor cores in dependence on a number of idle signals received from the data processor cores.
Claims26
A multi-core data processor comprising:
- a plurality of central processing unit (CPU) core modules, each having a first input for receiving a clock signal, a second input for receiving a power supply voltage, and an output for providing an idle signal;
- and
- a clock and power controller coupled to each of said plurality of CPU core modules for providing said clock signal and said power supply voltage to each of said plurality of CPU core modules, said clock and power controller providing at least one of said clock signal and said power supply voltage to an active one of said plurality of CPU core modules in dependence on a number of idle signals received from said plurality of CPU core modules.
A multi-core data processor comprising:
- a plurality of central processing unit (CPU) core modules;
- and
- a clock and power controller coupled to each of said plurality of CPU core modules for providing a clock signal and a power supply voltage to an active one of said plurality of CPU core modules having at least one of a voltage guardband of said power supply voltage and a frequency guardband of said clock signal determined in dependence on a number of idle signals received from said plurality of CPU core modules.
A clock and power controller for a multi-core data processor comprising:
- a power state controller for providing a power state number;
- and
- a power state table having an input for receiving said power state number, a first output for providing a frequency identification signal, and a second output for providing a voltage identification signal;
- a guardband determination circuit having an input for receiving a plurality of central processing unit (CPU) core idle signals, and an output for providing a voltage guardband offset in response to a number of idle CPU core idle signals;
- and
- an adder for adding said voltage guardband offset to said voltage identification signal to form a modified voltage identification signal.
A method comprising:
- determining a number of idle central processing unit (CPU) core modules of a multi-core data processor;
- calculating a guardband based on said number of idle CPU core modules;
- adjusting a selected one of a voltage identification signal or a frequency identification signal using said guardband;
- generating a clock signal for an active CPU core module using said frequency identification signal;
- and
- generating a power supply voltage for said active CPU core module using said voltage identification signal.
Dependencies are inferred from the claim text.