Heterogeneous multiprocessor design for power-efficient and area-efficient computing
AssigneeNVIDIA Corporation
InventorsGary D. Hicok, Matthew Raymond LONGNECKER, Rahul Gautam PATEL
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AssigneeNVIDIA Corporation
InventorsGary D. Hicok, Matthew Raymond LONGNECKER, Rahul Gautam PATEL
Estimating the term…
A technique for managing processor cores within a multi-core central processing unit (CPU) provides efficient power and resource utilization over a wide workload range. The CPU comprises at least one core designed for low power operation and at least one core designed for high performance operation. For low workloads, the low power core executes the workload. For certain higher workloads, the high performance core executes the workload. For certain other workloads, the low power core and the high performance core both share execution of the workload. This technique advantageously enables efficient processing over a wider range of workloads than conventional systems.
A method for configuring one or more cores within a processing unit for executing different workloads, the method comprising:
A computer-readable storage medium including instructions that, when executed by a processing unit, cause the processing unit to configure one or more cores within a processing unit for executing different workloads, the method comprising:
A computing device, comprising:
Dependencies are inferred from the claim text.