Computation Memory Operations in a Logic Layer of a Stacked Memory

An apparatus, comprising:

• a memory chip;
• and
• a logic chip coupled to the memory chip to form a memory device, wherein the logic chip is configured to:
• receive a compound instruction from a processor, wherein the computation instruction includes a memory access instruction and one or more multiple descriptors;
• decode the computation instruction to identify one or more data elements in the memory chip, the decoding being based on the one or more multiple descriptors;
• access the one or more data elements based on the memory access instruction;
• and;
• perform one or more computation operations on the one or more data elements.

A non-transitory computer-readable medium having stored thereon computer-executable instructions, execution of which by a computing device cause the computing device to perform operations comprising:

• receiving a computation instruction from a processor, wherein the computation instruction includes a memory access instruction and one or more multiple descriptors;
• decoding the computation instruction to identify one or more data elements in a memory chip, the decoding being based on the one or more multiple descriptors;
• accessing the one or more data elements based on the memory access instruction;
• and;
• performing one or more computation operations on the one or more data elements.