Compressing Execution Cycles For Divergent Execution In A Single Instruction Multiple Data (SIMD) Processor

A machine-readable medium having stored thereon instructions, which if performed by a machine cause the machine to perform a method comprising:

• receiving a single instruction multiple data (SIMD) instruction and information associated with the SIMD instruction in a SIMD execution unit of a processor, the SIMD instruction having a plurality of channels that are to consume a first plurality of execution cycles;
• identifying a first portion of the plurality of channels of the SIMD instruction that are to be disabled;
• harvesting one or more execution cycles of the first plurality of execution cycles based on the identifying;
• and
• after the harvesting, executing the SIMD instruction in fewer execution cycles than the first plurality of execution cycles.

A system comprising:

• a processor comprising:
• a core domain including a plurality of cores to independently execute instructions;
• and
• a graphics domain including a plurality of graphics processors to perform general purpose workloads offloaded by the core domain, each of the graphics processors having a vector execution unit including a plurality of lanes each to execute an operation on at least one data element of a plurality of data elements identified by a vector instruction, the vector execution unit to perform the vector instruction on the plurality of data elements in a first number of execution cycles, and a cycle compression logic coupled to the vector execution unit to reduce the first number of execution cycles;
• and
• a dynamic random access memory (DRAM) coupled to the processor.