US 2014/0181468 A1 · REGISTER FILES FOR A DIGITAL SIGNAL PROCESSOR OPERATING IN AN INTERLEAVED MULTI-THREADED ENVIRONMENT

Abstract

A processor device is disclosed and includes a memory and a sequencer that is responsive to the memory. The sequencer supports very long instruction word (VLIW) type instructions and at least one VLIW instruction packet uses a number of operands during execution. The processor device further includes a plurality of instruction execution units responsive to the sequencer and a plurality of register files. Each of the plurality of register files includes a plurality of registers and the plurality of register files are coupled to the plurality of instruction execution units. Further, each of the plurality of register files includes a number of data read ports and the number of data read ports of each of the plurality of register files is less than the number of operands used by the at least one VLIW instruction packet.

Claims19

Dependent claims

A method of operating a processor, the method comprising:

retrieving a first operand of a very long instruction word (VLIW) instruction from a first data read port of a register file coupled to the processor, during a first time period;
maintaining access to the register file via the first data read port during a second time period;
and
retrieving a second operand of the VLIW instruction from the first data read port during the second time period,
wherein the VLIW instruction comprises a total number of operands and the register file comprises a total number of data read ports, such that the total number of operands of the VLIW instruction is greater than the total number of data read ports of the register file.

2 more elements

An apparatus comprising:

a processor;
a memory coupled to the processor;
a register file coupled to the processor;
and
a sequencer configured to fetch a very long instruction word (VLIW) instruction from the memory and access the register file to retrieve operands of the VLIW instruction for execution of the VLIW instruction by the processor, wherein the sequencer is configured to:
retrieve a first operand of the VLIW instruction from a first data read port of the register file, during a first time period;
maintain access to the register file via the first data read port during a second time period;
and
retrieve a second operand of the VLIW instruction from the first data read port during the second time period,
wherein the VLIW instruction comprises a total number of operands and the register file comprises a total number of data read ports, such that the total number of operands of the VLIW instruction is greater than the total number of data read ports of the register file

7 more elements

A non-transitory computer-readable storage medium comprising code, which, when executed by a processor, causes the processor to perform operations related to execution of a very long instruction word (VLIW), the non-transitory computer-readable storage medium comprising:

code for retrieving a first operand of the VLIW instruction from a first data read port of a register file coupled to the processor, during a first time period;
code for maintaining access to the register file via the first data read port during a second time period;
and
code for retrieving a second operand of the VLIW instruction from the first data read port during the second time period,
wherein the VLIW instruction comprises a total number of operands and the register file comprises a total number of data read ports, such that the total number of operands of the VLIW instruction is greater than the total number of data read ports of the register file.

2 more elements

Dependencies are inferred from the claim text.

Register files for a digital signal processor operating in an interleaved multi-threaded environment

Life of this patent

Register files for a digital signal processor operating in an interleaved multi-threaded environment

Life of this patent

Abstract

Claims19