Processors having fully-connected interconnects shared by vector conflict instructions and permute instructions

A method comprising:

• receiving a permute instruction indicating at least a first source vector including at least four data elements and indicating a first destination storage location;
• conveying the at least four data elements of the first source vector through a fully-connected interconnect of a vector execution unit executing the permute instruction;
• receiving a vector conflict instruction indicating at least a second source vector including at least four data elements and indicating a second destination storage location;
• and
• conveying the at least four data elements of the second source vector through the fully-connected interconnect of the vector execution unit.

A system comprising:

• an interconnect;
• a processor coupled with the interconnect, the processor including an execution unit, the execution unit including:
• a fully-connected interconnect having at least four inputs to receive at least four corresponding data elements of at least one source vector, and at least four outputs, where each of the at least four inputs is coupled with each of the at least four outputs;
• a permute instruction execution logic coupled with the at least four outputs and operable to store a first vector result in response to a permute instruction;
• and
• a vector conflict instruction execution logic coupled with the at least four outputs and operable to store a second vector result in a destination storage location in response to a vector conflict instruction;
• and
• a dynamic random access memory (DRAM) coupled with the interconnect.