Memory, memory controller, memory system including the memory and the memory controller, and operating method of the memory system

A memory, comprising:

• a cell array configured to include a plurality of memory cells;
• first to Nth storage units configured to store a failed address;
• an internal address generation unit configured to generate an internal address by adding an external address and a conversion value, wherein the conversion value being a maximum value of K (1≦K<N) satisfying a condition that a sum of the external address and the K is greater than the failed address stored in the Kth storage unit of the first to the Nth storage units;
• and
• a control unit configured to access memory cells designated by the internal address among the plurality of memory cells in response to an access command.

An operating method of a memory system comprising a memory and a memory controller, comprising:

• counting a number of failed addresses in the memory, generating count information based on a result of the count, and applying the count information to the memory controller;
• setting a difference between an original maximum value and the count information as a maximum address value with the memory controller;
• and
• generating an address having a value between a minimum address value and the maximum address value with the memory controller.

A memory, comprising:

• a cell array configured to include a plurality of memory cells;
• a plurality of storage units configured to store a failed address;
• an address mapping unit configured to map an external address to an internal address having a different value from the failed address stored in the plurality of storage units;
• and
• a control unit configured to access memory cells designated by the internal address among the plurality of memory cells in response to an access command.

A memory system, comprising:

• a memory configured to include a plurality of memory cells, to access memory cells designated by an internal address among the plurality of memory cells in response to a plurality of command signals, to count a number of failed addresses, and to generate count information based on a result of the count;
• and
• a memory controller configured to set a maximum address value in response to the count information, to generate an address having a value between a minimum address value and the maximum address value, and to input the plurality of command signals and the generated address to the memory,
• wherein the memory maps an address, which is received from the memory controller, to the internal address so that the received address has a different value from the failed address.