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US 2014/0181449 A1Published application
Memory controller and memory system including the same
AssigneeSK hynix Inc.
InventorsYong Kee KWON, Hyung Dong LEE, Young Suk MOON, Hyung Gyun YANG
Life of this patent
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Abstract
A memory system includes a memory unit and a memory controller. The memory unit includes a plurality of memory banks, wherein an information stored in a memory bank is accessed via a word line and a bit line. The memory controller is configured to limit repetitive accessing of a same word line or a same bit line so that the number of consecutive access is less than a predetermined critical value.
Claims26
A memory system comprising:
- a memory unit comprising a plurality of memory banks, wherein an information stored in a memory bank is accessed via a word line and a bit line;
- and
- a memory controller configured to limit repetitive accessing of a same word line or a same bit line so that the number of consecutive access is less than a predetermined critical value.
A memory controller comprising:
- an address mapping unit configured to receive a physical address and generate a pre-address signal;
- an access control unit configured to generate an address signal from the pre-address signal, and delay the generation of the address signal by a predetermined time when a same pre-address signals are consecutively and repetitively inputted by a number exceeding a critical value;
- and
- an arbiter configured to receive the address signal and provide the address signal to a memory unit.
1 more element
A memory system comprising:
- a memory unit comprising a plurality of memory banks;
- and
- a memory controller configured to access the memory unit,
- wherein the memory controller comprises:
- an address mapping unit configured to receive a physical address and generate a pre-address signal;
- an access control unit configured to generate an address signal from the pre-address signal, and delay the generation of the address signal by a predetermined time when the same pre-address signals are consecutively and repetitively inputted by a number exceeding a critical value;
- and
- an arbiter configured to provide the address signal to the memory unit.
5 more elements
A system comprising:
- a processor;
- a controller configured to receive a request and a data from the processor;
- and
- a memory unit configured to receive a controlled request and the data from the controller,
- wherein the controller is configured to generate the controlled request, when the request for accessing a predetermined word line and a predetermined bit line of the memory unit is consecutively and repetitively generated.
2 more elements
A system comprising:
- a processor
- a chipset configured to couple with the processor;
- a controller configured to receive a request provided from the processor through the chipset;
- a memory device configured to receive a controlled request and the data from the controller;
- and
- an I/O device configured to couple with the chipset,
- wherein the controller is configured to generate the controlled request, when the request for accessing a predetermined word line and a predetermined bit line of the memory unit is consecutively and repetitively generated.
4 more elements
A memory system comprising:
- a memory unit comprising a plurality of memory banks, wherein an information stored in a memory bank is accessed via a word line and a bit line;
- and
- a memory controller configured to limit repetitive accessing of a same word line or a same bit line over a predetermined time period.
Dependencies are inferred from the claim text.