US 2014/0181427 A1 · Compound Memory Operations in a Logic Layer of a Stacked Memory

Abstract

Some die-stacked memories will contain a logic layer in addition to one or more layers of DRAM (or other memory technology). This logic layer may be a discrete logic die or logic on a silicon interposer associated with a stack of memory dies. Additional circuitry/functionality is placed on the logic layer to implement functionality to perform various data movement and address calculation operations. This functionality would allow compound memory operations—a single request communicated to the memory that characterizes the accesses and movement of many data items. This eliminates the performance and power overheads associated with communicating address and control information on a fine-grain, per-data-item basis from a host processor (or other device) to the memory. This approach also provides better visibility of macro-level memory access patterns to the memory system and may enable additional optimizations in scheduling memory accesses.

Claims29

Dependent claims

A method, comprising:

receiving, by a logic chip, a compound instruction from a processor, wherein the compound instruction includes a memory access instruction and one or more descriptors;
decoding, by the logic chip, the compound instruction to provide addresses of two or more data elements in a memory chip, wherein the decoding is based on the one or more descriptors;
and
accessing the two or more data elements based on the memory access instruction.

1 more element

Dependencies are inferred from the claim text.

Compound Memory Operations in a Logic Layer of a Stacked Memory

Life of this patent

Compound Memory Operations in a Logic Layer of a Stacked Memory

Life of this patent

Abstract

Claims29