Processing engine for complex atomic operations
AssigneeAdvanced Micro Devices, Inc.
InventorsJames M. O'CONNOR, Michael J. Schulte, Nuwan S. Jayasena, Gabriel H. Loh
Life of this patent
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Abstract
A system includes an atomic processing engine (APE) coupled to an interconnect. The interconnect is to couple to one or more processor cores. The APE receives a plurality of commands from the one or more processor cores through the interconnect. In response to a first command, the APE performs a first plurality of operations associated with the first command. The first plurality of operations references multiple memory locations, at least one of which is shared between two or more threads executed by the one or more processor cores.
Claims20
A system, comprising:
- an interconnect to couple to one or more processor cores;
- and
- an atomic processing engine (APE), coupled to the interconnect, to receive a plurality of commands from the one or more processor cores through the interconnect and, in response to a first command of the plurality of commands, perform a first plurality of operations associated with the first command, the first plurality of operations referencing multiple memory locations;
- wherein at least one of the multiple memory locations is shared between a plurality of threads to be executed by the one or more processor cores.
A method, comprising:
- in an atomic processing engine (APE), receiving a first command from a first thread of a plurality of threads executing on one or more processor cores;
- and
- in the APE, performing a first plurality of operations associated with the first command, the first plurality of operations referencing multiple memory locations, wherein at least one of the multiple memory locations is shared between the first thread and at least one other thread of the plurality of threads.
A non-transitory computer-readable storage medium storing instructions, which when executed by a respective processor core of one or more processor cores, cause the respective processor core to issue a command to an atomic processing engine to perform a plurality of operations referencing multiple memory locations;
- wherein at least one of the multiple memory locations is shared between a plurality of threads to be executed by the one or more processor cores.
Dependencies are inferred from the claim text.