Credit lookahead mechanism
AssigneeApple Inc.
InventorsGurjeet S. Saund, Harshavardhan Kaushikkar, Benjamin K. Dodge
Life of this patent
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Abstract
Systems and methods for preventing excessive buffering of transactions in a coherence point. The coherence point uses a lookahead mechanism to determine if there are enough credits from the memory controller for forwarding the outstanding transactions stored in the IRQ. If there are not enough credits, then the coherence point prevents the switch fabric from forwarding additional transactions to the coherence point. By preventing excessive buffering in the IRQ, the QoS-based ordering of transactions performed by the switch fabric is preserved.
Claims24
A coherence point comprising an input request queue (IRQ), wherein the coherence point is configured to:
- monitor a first number of credits received from a memory controller;
- determine a second number of credits needed to service outstanding transactions stored in the IRQ;
- compare the first and second number of credits;
- and
- prevent additional transactions from being sent to the coherence point responsive to determining a difference between the first and second number of credits is less than a predetermined threshold.
A method comprising:
- monitoring a first number of credits received by a coherence point for sending transactions to a memory controller;
- determining a second number of credits needed by outstanding transactions in a queue in the coherence point;
- determining if a difference between the first and second numbers of credits is less than a predetermined threshold;
- and
- stalling transactions at a switch fabric responsive to determining the difference is less than the predetermined threshold.
A method comprising:
- maintaining a count of a number of available credits in a coherence point, wherein the number of available credits is equal to a number of credits received from a memory controller in excess of a number of credits needed by transactions waiting to be sent to the memory controller from the coherence point;
- decrement the count responsive to receiving a first transaction from a switch fabric;
- increment the count responsive to detecting a hit in level two (L2) duplicate tags for the first transaction;
- and
- sending a stall signal to the switch fabric responsive to determining the count is less than a predetermined threshold.
A system on chip (SoC) comprising:
- a memory controller;
- a coherence point, wherein the coherence point comprises an input request queue (IRQ) for storing transactions;
- and
- a switch fabric;
- wherein the memory controller is configured to send credits to the coherence point, wherein credits are needed for forwarding transactions from the coherence point to the memory controller;
- wherein the coherence point is configured to:
- monitor a number of credits received from the memory controller;
- monitor a number of transactions stored in the IRQ;
- compare the number of credits to the number of transactions;
- and
- prevent additional transactions from being sent to the coherence point responsive to determining a difference between the number of credits and the number of transactions is less than a predetermined threshold.
Dependencies are inferred from the claim text.