US 2014/0181417 A1 · CACHE COHERENCY USING DIE-STACKED MEMORY DEVICE WITH LOGIC DIE

Abstract

A die-stacked memory device implements an integrated coherency manager to offload cache coherency protocol operations for the devices of a processing system. The die-stacked memory device includes a set of one or more stacked memory dies and a set of one or more logic dies. The one or more logic dies implement hardware logic providing a memory interface and the coherency manager. The memory interface operates to perform memory accesses in response to memory access requests from the coherency manager and the one or more external devices. The coherency manager comprises logic to perform coherency operations for shared data stored at the stacked memory dies. Due to the integration of the logic dies and the memory dies, the coherency manager can access shared data stored in the memory dies and perform related coherency operations with higher bandwidth and lower latency and power consumption compared to the external devices.

Claims26

Dependent claims

An integrated circuit (IC) package comprising:

a die-stacked memory device comprising:
a set of one or more stacked memory dies implementing memory cell circuitry;
and
a set of one or more logic dies electrically coupled to the memory cell circuitry, the set of one or more logic dies comprising a coherency manager and a memory interface, the memory interface coupled to the coherency manager and coupleable to a device external to the die-stacked memory device, and the coherency manager to maintain coherency for memory addresses mapped to the set of one or more stacked memory dies.

1 more element

A method comprising:

providing an integrated circuit (IC) comprising a set of one or more stacked memory dies comprising memory cell circuitry and comprising a set of one or more logic dies electrically coupled to the set of one or more stacked memory dies, the set of one or more logic dies comprising a coherency manager coupled to the memory cell circuitry of the set of one or more stacked memory dies and comprising a memory interface coupled to the coherency manager and coupled to one or more external devices;
operating the memory interface to perform memory accesses for the device;
and
operating the coherency manager to maintain coherency for memory addresses mapped to the set of one or more stacked memory dies.

1 more element

A computer readable storage medium storing code that is operable to manipulate at least one computer system to perform a portion of a process to fabricate an integrated circuit (IC) package, the IC package comprising:

a die-stacked memory device comprising:
a set of one or more stacked memory dies implementing memory cell circuitry;
and
a set of one or more logic dies electrically coupled to the memory cell circuitry, the set of one or more logic dies comprising a coherency manager and a memory interface, the memory interface coupled to the coherency manager and coupleable to a device external to the die-stacked memory device, and the coherency manager to maintain coherency for memory addresses mapped to the set of one or more stacked memory dies.

1 more element

Dependencies are inferred from the claim text.

Cache coherency using die-stacked memory device with logic die

Life of this patent

Cache coherency using die-stacked memory device with logic die

Life of this patent

Abstract

Claims26