Processing device with independently activatable working memory bank and methods

A method of data processing comprising:

• providing a processing component having a processing engine associated with an array of working memory banks that includes an independently activatable memory bank;
• establishing a dirty data count that reflects dirty data migrated from the independently activatable memory bank upon selective deactivation of the independently activatable memory bank;
• and
• selectively decrementing the dirty data count upon the reactivation of the independently activatable memory bank in connection with a transient state wherein each access for dirty data by the processing engine to the independently activatable memory bank is also conducted with respect to another memory bank of the array and upon a condition that the dirty data is found in the other memory bank, the count of dirty data is decremented.

A non-transitory computer-readable storage medium storing a set of instructions for execution by a general purpose computer to facilitate manufacture of an integrated circuit that includes:

• a processing component having:
• an array of working memory banks associated with a processing engine;
• a dirty data counter (DDC) associated with an independently activatable memory bank within the array;
• the DDC configured to reflect a count of dirty data migrated from the independently activatable memory bank upon selective deactivation of the independently activatable memory bank;
• and
• the DDC configured to selectively decrement the count of dirty data upon the reactivation of the independently activatable memory bank in connection with a transient state wherein each access for dirty data by the processing engine to the independently activatable memory bank is also conducted with respect to another memory bank of the array and upon a condition that the dirty data is found in the other memory bank, the count of dirty data is decremented.