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AssigneeAdvanced Micro Devices, Inc.
InventorsJohn Kalamatianos, Edward J. McLellan, Paul Keltcher, Srilatha Manne, Richard E. Klass, James M. O'Connor
Estimating the term…
In response to a processor core exiting a low-power state, a cache is set to a minimum size so that fewer than all of the cache's entries are available to store data, thus reducing the cache's power consumption. Over time, the size of the cache can be increased to account for heightened processor activity, thus ensuring that processing efficiency is not significantly impacted by a reduced cache size. In some embodiments, the cache size is increased based on a measured processor performance metric, such as an eviction rate of the cache. In some embodiments, the cache size is increased at regular intervals until a maximum size is reached.
A method, comprising:
A method, comprising:
A processor, comprising:
A computer readable medium storing code to adapt at least one computer system to perform a portion of a process to fabricate at least part of a processor, the processor comprising:
Dependencies are inferred from the claim text.