Way preparation for accessing a cache
AssigneeAdvanced Micro Devices, Inc.
InventorsMatthew M. Crum, Teik-Chung Tan
Life of this patent
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Abstract
For a memory access at a processor, only a subset (less than all) of the ways of a cache associated with a memory address is prepared for access. The subset of ways is selected based on stored information indicating, for each memory access, which corresponding way of the cache was accessed. The subset of ways is selected and preparation of the subset of ways is initiated prior to the final determination as to which individual cache way in the subset is to be accessed.
Claims25
A method of accessing a cache comprising a plurality of ways, the method comprising:
- storing access information for a first memory access indicating a subset of the plurality of ways, one of the subset accessed by the first memory access;
- in response to a second memory access to the plurality of ways:
- determining the subset of the plurality of ways based on the access information;
- and
- preparing the subset of the plurality of ways for access concurrent with determining a memory address based on the second memory access.
A method of accessing a cache comprising a plurality of ways, comprising:
- determining a memory address based on memory address components associated with a memory request;
- concurrent with determining the memory address, predicting based on the memory address components a selected way of the plurality of ways as the way to be accessed by the memory request and preparing the selected way for access based on the predicting;
- and
- concurrent with predicting the selected way, determining a subset of the plurality of ways based on the memory address and preparing the subset of the plurality of ways for access.
A processor, comprising:
- a cache comprising a plurality of ways;
- a storage location to store a vector indicating a subset of the plurality of ways accessed by a first memory access;
- an address generation unit to determine a memory address in response to receiving a second memory access;
- a partial set predictor to, in response to the second memory access, determine the subset of the plurality of ways based on the vector;
- and
- a controller to prepare the subset of the plurality of ways for access concurrent with the address generation unit determining the memory address.
A computer readable medium storing code to adapt at least one computer system to perform a portion of a process to fabricate at least part of a processor, the processor comprising:
- a cache comprising a plurality of ways;
- a storage location to store a vector indicating a subset of the plurality of ways accessed by a first memory access;
- an address generation unit to determine a memory address in response to receiving a second memory access;
- a partial set predictor to, in response to the second memory access, determine the subset of the plurality of ways based on the vector;
- and
- a controller to prepare the subset of the plurality of ways for access concurrent with the address generation unit determining the memory address.
Dependencies are inferred from the claim text.