Instruction cache having a multi-bit way prediction mask
AssigneeQUALCOMM Incorporated
InventorsPeter G. Sassone, Suresh K. Venkumahanti, Lucian Codrescu
Life of this patent
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Abstract
In a particular embodiment, an apparatus includes control logic configured to selectively set bits of a multi-bit way prediction mask based on a prediction mask value. The control logic is associated with an instruction cache including a data array. A subset of line drivers of the data array is enabled responsive to the multi-bit way prediction mask. The subset of line drivers includes multiple line drivers.
Claims24
An apparatus comprising:
- control logic configured to selectively set bits of a multi-bit way prediction mask based on a prediction mask value, the control logic associated with an instruction cache including a data array,
- wherein a subset of line drivers of the data array is enabled responsive to the multi-bit way prediction mask, the subset of line drivers including multiple line drivers.
A method comprising:
- selectively setting bits of a multi-bit way prediction mask based on a prediction mask value, the multi-bit way prediction mask associated with an instruction cache including a data array having a plurality of line drivers;
- wherein a subset of line drivers of the plurality of line drivers is enabled responsive to the multi-bit way prediction mask, the subset of line drivers including multiple line drivers.
An apparatus comprising:
- means for selectively setting bits of a multi-bit way prediction mask based on a prediction mask value, the multi-bit way prediction mask associated with an instruction cache including a data array;
- and
- means for providing the multi-bit way prediction mask to a plurality of line drivers of the data array;
- wherein multiple line drivers of the plurality of line drivers are enabled. responsive to the multi-bit way prediction mask.
A non-transitory computer readable medium comprising instructions that when executed by a processor, cause the processor to:
- selectively set bits of a multi-bit way prediction mask according to a prediction mask value, the multi-bit way prediction mask associated with an instruction cache including a data array;
- wherein multiple line drivers of the data array are enabled responsive to the multi-bit way prediction mask.
Dependencies are inferred from the claim text.