Memory Systems and Methods for Dynamically Phase Adjusting a Write Strobe and Data to Account for Receive-Clock Drift
AssigneeRambus Inc.
InventorFrederick A. Ware
Life of this patent
Estimating the term…
Abstract
A memory system includes a memory controller that writes data to and reads data from a memory device. A write data strobe accompanying the write data indicates to the memory device when the write data is valid, whereas a read strobe accompanying data from the memory device indicates to the memory controller when the read data is valid. The memory controller adaptively controls the phase of the write data strobe to compensate for timing drift at the memory device. The memory controller uses read signals as a measure of the drift.
Claims20
(canceled)
A method of operation of a memory controller to control a memory device, the method comprising:
- generating a read-clock signal of a read-clock phase;
- issuing read commands to the memory device to obtain read data;
- capturing the read data timed to the read-clock phase;
- tracking a time interval since a last of the read commands;
- issuing a supplemental read command if the time interval exceeds a predetermined value;
- receiving a supplemental read signal of a read phase responsive to the supplemental read command;
- and
- adjusting the read-clock phase responsive to the read phase.
A memory controller for controlling a memory device, the memory controller comprising:
- control logic to issue read commands;
- a command interface coupled to the control logic to convey the read commands to the memory device;
- and
- a variable-delay read circuit having a first input to receive a read-clock signal and a second input to receive read data, the variable-delay read circuit to phase align the read-clock signal with the read data and sample the read data in time with the phase-aligned read-clock signal;
- wherein the control logic tracks a time interval since the last of the read commands and issues a supplemental read command to the memory device if the time interval exceeds a predetermined value.
A method of operation of a memory controller to control a memory device, the method comprising:
- generating a read-clock signal of a read-clock phase;
- issuing read commands to the memory device to obtain read-data signals, read-strobe signals, and read-phase information;
- updating the read-clock phase responsive to the read-phase information;
- capturing the read data timed to the read-clock phase;
- and
- occasionally issuing supplemental read commands to obtain the read-phase information.
Dependencies are inferred from the claim text.