Hardware chip select training for memory using write leveling mechanism

A computer readable storage medium having stored thereon, computer executable instructions that, if executed by a computer system cause the computer system to perform a method of training chip select for a memory module, said method comprising:

• a) programming a memory controller into a mode wherein a command signal is active for a programmable time period;
• b) programming a programmable delay line of said chip select with a delay value;
• c) performing initialization of said memory module;
• d) placing said memory module in a write leveling mode wherein said placing toggles a state of said chip select;
• e) performing a write leveling procedure and determining a response thereto from said memory module;
• and
• f) determining whether said memory module is in a pass state or an error state based on said response.

A system comprising:

• a processor coupled to a computer readable storage media using a bus and executing computer readable code which causes the computer system to perform a method of training chip select for a memory module, said method comprising:
• a) programming a memory controller into a mode wherein a command signal is active for a programmable time period;
• b) programming a programmable delay line of said chip select with a delay value;
• c) performing initialization of said memory module;
• d) placing said memory module in a write leveling mode wherein said placing toggles a state of said chip select;
• e) performing a write leveling procedure and determining a response thereto from said memory module;
• and
• f) determining whether said memory module is in a pass state or an error state based on said response.