Back to results
US 2014/0181390 A1Published application
Method, apparatus and system for exchanging communications via a command/address bus
AssigneeIntel Corporation
InventorsKuljit S. Bains, James A. McCall
Life of this patent
Estimating the term…
Abstract
Techniques and mechanisms for exchanging information from a memory controller to a memory device via a command/address bus. In an embodiment, the memory device samples a first portion of a command during a first sample period and samples a second portion of the command during a second sample period, the first portion and second portion exchanged via the command/address bus. The first sample period and the second sample period are concurrent with, respectively, a first transition of a clock signal and a second transition of the clock signal. In another embodiment, a mode of the memory device determines a relationship between the first transition and the second transition.
Claims30
A memory device comprising:
- a mode register to store a value identifying a mode of operation of the memory device;
- and
- command/address (CA) logic to determine the mode based on the value and, based on the mode, to sample a command provided by a memory controller coupled to the memory device, including:
- the CA logic to sample a first portion of the command provided via a command/address bus during a first period, wherein a middle of the first period is synchronized with a first transition of a first clock signal provided by the memory controller;
- and
- the CA logic to sample a second portion of the command provided via the command/address bus during a second period, wherein a middle of the second period is synchronized with a second transition of the first clock signal;
- wherein if the determined mode is a first mode, then the second transition is an Nth transition of the first clock signal after the first transition, wherein N is an integer greater than one, and if the determined mode is a second mode, the second transition is a next transition of the first clock signal after the first transition.
4 more elements
A method at a memory device, the method comprising:
- determining a mode of operation based on a mode register of the memory device;
- and
- based on the determined mode, sampling a command provided by a memory controller coupled to the memory device, including:
- sampling a first portion of the command provided via a command/address bus during a first period, wherein a middle of the first period is synchronized with a first transition of a first clock signal provided by the memory controller;
- and
- sampling a second portion of the command provided via the command/address bus during a second period, wherein a middle of the second period is synchronized with a second transition of the first clock signal;
- wherein if the determined mode is a first mode, then the second transition is an Nth transition of the first clock signal after the first transition, wherein N is an integer greater than one, and if the determined mode is a second mode, the second transition is a next transition of the first clock signal after the first transition.
4 more elements
A memory controller comprising:
- configuration logic to determine a mode of operation of a memory device coupled to the memory controller;
- and
- scheduler logic to schedule communication of a command to the memory device based on the determined mode, including:
- the scheduler logic to schedule communication of a first portion of the command via a command/address bus for a first period, wherein a middle of the first period is synchronized with a first transition of a first clock signal provided by the memory controller to the memory device;
- and
- the scheduler logic to schedule communication of a second portion of the command via the command/address bus for a second period, wherein a middle of the second period is synchronized with a second transition of the first clock signal;
- wherein if the determined mode is a first mode, then the second transition is an Nth transition of the first clock signal after the first transition, wherein N is an integer greater than one, and if the determined mode is a second mode, the second transition is a next transition of the first clock signal after the first transition.
4 more elements
A method at a memory controller, the method comprising:
- determining a mode of operation of a memory device coupled to the memory controller
- scheduling communication of a command to the memory device based on the determined mode, including:
- scheduling communication of a first portion of the command via a command/address bus for a first period, wherein a middle of the first period is synchronized with a first transition of a first clock signal provided by the memory controller to the memory device;
- and
- scheduling communication of a second portion of the command via the command/address bus for a second period, wherein a middle of the second period is synchronized with a second transition of the first clock signal;
- wherein if the determined mode is a first mode, then the second transition is an Nth transition of the first clock signal after the first transition, wherein N is an integer greater than one, and if the determined mode is a second mode, the second transition is a next transition of the first clock signal after the first transition.
3 more elements
Dependencies are inferred from the claim text.