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US 2014/0181380 A1Published application
Memory wear control
AssigneeSeagate Technology LLC
InventorsTimothy Richard Feldman, Jonathan Williams Haines, Brett Alan Cook
Life of this patent
Estimating the term…
Abstract
The disclosure is related to systems and methods of controlling wear of a memory. In a particular embodiment, a system is disclosed that comprises a memory and a performance governor circuit coupled to the memory. The performance governor circuit is adapted to control a wear of the memory as a function of time.
Claims20
A system comprising:
- a performance governor circuit configured to connect to a memory and configured to control a degree of wear of the memory as a function of at least one selected point in time by:
- computing a wear value of a new command;
- determining whether the computed wear value will cause a current memory wear to exceed a predetermined wear level;
- and
- if the computed wear value will not cause the current memory wear to exceed the predetermined wear level within a smallest possible command completion time of the new command, then executing the new command.
2 more elements
A system comprising:
- a performance governor circuit configured to connect to a memory and configured to control a degree of wear of the memory as a function of at least one selected point in time by:
- determining a wear effect of executing a new command to access the memory on a current memory wear, and
- controlling execution of the new command based on the determined wear effect and based on a smallest possible command completion time of the new command.
A method comprising:
- receiving commands to access a memory;
- computing wear values for the received commands;
- and
- executing the received commands, based on the computed wear values and based on a smallest command completion time of each of the received commands, at a rate that maintains a wear of the memory at or below a wear versus time profile.
1 more element
Dependencies are inferred from the claim text.