Memory controller

Abstract

According to one embodiment, a memory controller includes a first interface, a second interface, a cache unit, a translation unit, an access unit and a lock unit. The first interface receives a lock request and an access request which includes a logical address. The second interface is connectable to a non-volatile memory. The cache unit comprises a plurality of cache line and caches correspondence information between the logical address and a physical address of the non-volatile memory. The translation unit translates the logical address included in the access request into the physical address with reference to the cache unit. The access unit performs access in accordance with the access request to a position indicated by the translated physical address. The lock unit sets the cache line lock state in accordance with the lock request. The lock state is the state where the cache line being prohibited to be refilled.

Dependencies are inferred from the claim text.