Data reading method, memory controller, and memory storage device

A memory storage device, comprising:

• a connector, configured to couple to a host system;
• a rewritable non-volatile memory module, comprising a plurality of physical erasing units;
• and
• a memory controller, coupled to the connector and the rewritable non-volatile memory module, configured to configure a plurality of logical addresses to be mapped to a part of the physical erasing units, and to receive a plurality of first read commands from the host system, wherein the first read commands instruct to read a plurality of first logical addresses among the logical addresses,
• wherein the memory controller is configured to execute the first read commands and determine whether the first logical addresses are successive,
• if the first logical addresses are successive, the memory controller is configured to pre-read data belonging to a first logical range among the logical addresses from the physical erasing units into a buffer memory.

A memory controller, for controlling a rewritable non-volatile memory module, the memory controller comprising:

• a host interface, configured to couple to a host system;
• a memory interface, configured to couple to the rewritable non-volatile memory module, wherein the rewritable non-volatile memory module comprises a plurality of physical erasing units;
• and
• a memory management circuit, coupled to the host interface and the memory interface, configured to configure a plurality of logical addresses to be mapped to a part of the physical erasing units, and to receive a plurality of first read commands from the host system, wherein the first read commands instruct to read a plurality of first logical addresses among the logical addresses,
• wherein the memory management circuit is configured to execute the first read commands and determine whether the first logical addresses are successive,
• if the first logical addresses are successive, the memory management circuit is configured to pre-read data belonging to a first logical range among the logical addresses from the physical erasing units into a buffer memory.