Crosstalk aware decoding for a data bus

An electronic device, comprising:

• a bus comprising a plurality of signal lines;
• a first signaling module coupled to a plurality of digital inputs, the first signaling module to encode data received at the plurality of digital inputs and drive signals on the plurality of signal lines of the bus, wherein each one of the plurality of signals corresponds to a weighted sum of the data received at the plurality of digital inputs;
• and
• a second signaling module coupled to the plurality of signal lines of the bus, the second signaling module to decode the plurality of signals received over the bus and generate a corresponding plurality of digital outputs, wherein the values of the plurality of digital outputs are equal to the values of the plurality of digital inputs, the second signaling module comprising:
• a receiver to receive a plurality of encoded line voltages or currents on a plurality of signal lines;
• a quantizer to determine signal levels of each of the plurality of signal lines at a unit interval;
• and
• an arithmetic circuit to provide a plurality of digital output bits of the decoder based on the signal levels, wherein each one of the digital output bits is a mathematical combination of all of the signal levels.

An electronic device, comprising:

• logic to receive a plurality of encoded line voltages or currents on a plurality of signal lines;
• logic to determine signal levels of each of the plurality of signal lines at a unit interval;
• and
• logic to provide a plurality of digital output bits of the decoder based on the signal levels, wherein each one of the digital output bits is a mathematical combination of all of the signal levels.