Crosstalk aware encoding for a data bus

The integrated circuit chip of claim 5, wherein the decoder decodes the signal data using a decoding matrix that is the transpose of the encoding matrix.

An electronic device, comprising:

• a bus comprising a plurality of signal lines;
• a first signaling module coupled to a plurality of digital inputs, the first signaling module to encode data received at the plurality of digital inputs and drive signals on the plurality of signal lines of the bus, wherein each one of the plurality of signals corresponds to a weighted sum of the data received at the plurality of digital inputs;
• a second signaling module coupled to the plurality of signal lines of the bus, the second signaling module to decode the plurality of signals received over the bus and generate a corresponding plurality of digital outputs, wherein the values of the plurality of digital outputs are equal to the values of the plurality of digital inputs.

An electronic device, comprising:

• logic to receive a plurality of data bits in parallel, wherein each data bit corresponds to a different data stream and the plurality of data bits comprises a first data bit;
• logic to weight each of the data bits to generate weighted data;
• logic to sum the weighted data and generate, based on the sum of the weighted data, a signal level to transmit over a signal line, wherein the signal level is to be decoded to reproduce the first data bit.

A system comprising:

• a bus comprising a plurality of signal lines;
• a first transmitting module coupled to a plurality of digital inputs, the first transmitting module to encode data received at the plurality of digital inputs and drive signals on the plurality of signal lines of the bus, wherein each one of the plurality of signals corresponds to a weighted sum of the data received at the plurality of digital inputs.