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AssigneeInternational Business Machines Corporation
InventorToshiyuki Shiratori
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A controller for controlling interrupt processing in a multiple-interrupt system is provided. The controller includes multiple watchdog timers (WDTs), each provided for each of interrupt priorities. The controller includes interrupt priority selectors, each of which receives each interrupt request signal and outputs an activation signal to a corresponding WDT according to the priority of the interrupt request signal. The controller includes an interrupt processing circuit, which when a WDT has timed out, outputs, to a processor, an interrupt request signal having a priority one or more levels higher than the priority corresponding to the WDT. When multiple causes of interrupt are assigned to one of the interrupt priorities, the interrupt processing circuit gives priority to an interrupt request signal caused by the timeout of a WDT lower in priority level than the interrupt priority to detect that an abnormal operation has occurred in interrupt processing having the lower level priority.
A method, in a data processing system, of detecting an abnormal operation caused by interrupt processing in a multiple interrupt system, comprising:
A controller, in a data processing system, for controlling interrupt processing in a multiple-interrupt system, comprising:
Dependencies are inferred from the claim text.