Arithmetic circuit and arithmetic method
AssigneeKabushiki Kaisha Toshiba
InventorKoichiro BAN
Life of this patent
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Abstract
According to one embodiment, an arithmetic circuit includes follows. The arithmetic unit performs an arithmetic operation including addition and multiplication to generate a first value of (n+m) bits. The rounding preprocessor performs an OR operation on lower (m−k) bits of the first value to generate a second value of 1 bit. The register stores a third value of (n+k+1) bits obtained by concatenating upper (n+k) bits of the first value and the second value. The rounding postprocessor calculates a carry bit value of 1 bit from a most significant bit of the third value and lower (k+1) bits of the third value, and adds the carry bit value to upper n bits of the third value.
Claims14
An arithmetic circuit comprising:
- an arithmetic unit configured to perform an arithmetic operation including addition and multiplication to generate a first value of (n+m) bits, where n is an integer of not less than 1 and m is an integer of not less than 2;
- a rounding preprocessor configured to perform an OR operation on lower (m−k) bits of the first value to generate a second value of 1 bit, where k is an integer of not less than 1 and not more than (m−1);
- a register which stores a third value of (n+k+1) bits obtained by concatenating upper (n+k) bits of the first value and the second value;
- and
- a rounding postprocessor configured to calculate a carry bit value of 1 bit from a most significant bit of the third value and lower (k+1) bits of the third value, and add the carry bit value to upper n bits of the third value.
An arithmetic method comprising:
- performing an arithmetic operation including addition and multiplication to generate a first value of (n+m) bits, where n is an integer of not less than 1 and m is an integer of not less than 2;
- performing an OR operation on lower (m−k) bits of the first value to generate a second value of 1 bit, where k is an integer of not less than 1 and not more than (m−1);
- storing, in a register, a third value of (n+k+1) bits obtained by concatenating upper (n+k) bits of the first value and the second value;
- and
- calculating a carry bit value of 1 bit from a most significant bit of the third value and lower (k+1) bits of the third value, and adding the carry bit value to upper n bits of the third value.
An arithmetic circuit comprising:
- an arithmetic unit configured to perform an arithmetic operation including addition and multiplication to generate a first value of (n+m) bits, where n is an integer of not less than 1 and m is an integer of not less than 2;
- a rounding preprocessor configured to perform an OR operation on lower (m−1) bits of the first value to generate a second value of 1 bit;
- a register which stores a third value of (n+2) bits obtained by concatenating upper (n+1) bits of the first value and the second value;
- and
- a rounding postprocessor configured to determine an addition value of 2 bit based on a most significant bit of the third value, add the addition value to the third value to generate a fourth value, and remove lower two bits of the fourth value.
An arithmetic method comprising:
- performing an arithmetic operation including addition and multiplication to generate a first value of (n+m) bits, where n is an integer of not less than 1 and m is an integer of not less than 2;
- performing an OR operation on lower (m−1) bits of the first value to generate a second value of 1 bit;
- storing, in a register, a third value of (n+2) bits obtained by concatenating upper (n+1) bits of the first value and the second value;
- and
- determining an addition value of 2 bit based on a most significant bit of the third value, adding the addition value to the third value to generate a fourth value, and removing lower two bits of the fourth value.
Dependencies are inferred from the claim text.