Method and apparatus for detecting interference in design environment
AssigneeGehry Technologies, Inc.
InventorsJaemin LEE, Jim Chi-Kwan CHEUNG, Dennis SHELDEN
Life of this patent
Estimating the term…
Abstract
The disclosure provides a solution for clash detection in three-dimensional design by allowing multiple members to work on a centrally-located version of the model. The disclosure also provides massively-parallel processing of the design file which enables rapid processing and version control. The model can be maintained at one or more remote servers with significantly higher processing capability. Implementing clash detection on the remote server allows the system to take advantage of parallel processing. Complex 3D models can be identified and divided across multiple computational units to significantly increase processing speed.
Claims23
An apparatus for detecting interference between components in a design, the apparatus comprising:
- a processor circuit in communication with a memory circuit, the memory circuit providing instructions for the processor to:
- receive a first file containing a plurality of first design components, the plurality of first design components defining a first design aspect;
- receive a second file containing a plurality of second design components, the plurality of second design components defining a second design aspect;
- convert the first file and the second file to have neutral formats;
- identify a reference point common to the plurality of first design components and the plurality of second design components;
- overlay the first plurality of components over the second plurality of components to form a master file;
- identify an interference between at least one of the first plurality of components and one of the second plurality of components;
- and
- report the identified interference.
An apparatus for detecting interference between components in a design, the apparatus comprising:
- a processor circuit in communication with a memory circuit, the memory circuit providing instructions for the processor to:
- receive a first file containing a plurality of first design components, the plurality of first design components defining a first design aspect;
- receive a second file containing a plurality of second design components, the plurality of second design components defining a second design aspect;
- identify a reference point common to the plurality of first design components and the plurality of second design components;
- resolve the first plurality of components over the second plurality of components to form a compiled file;
- partition the complied file into a plurality of spatially independent portions, each spatially independent portion defining at least one of the first or the second plurality of components;
- defining a bounding box for each of the plurality of the first components and the second components;
- identify an interference between two discrete components when the distance between two adjacent bounding boxes is below a minimum threshold value.
A method for detecting interference between components in a design, the apparatus comprising:
- at a processor circuit in communication with a memory circuit, receiving a design file containing a plurality of discrete components resolved relative to each other;
- partitioning the design components into a first spatially independent partitions, each of the first partitions containing at least one of the plurality of discrete components;
- subdividing one of the first spatially independent partitions into a plurality of second spatially independent partitions;
- forming a plurality of bounding boxes, each bounding box enclosing a respective component of the first or the second spatially independent partitions;
- and
- identifying an interference between two discrete components when a distance between two adjacent bounding boxes is below a threshold value.
Dependencies are inferred from the claim text.