Method of manufacturing semiconductor device

A method of manufacturing a semiconductor device, comprising:

• forming a gate group including a plurality of gate patterns on a substrate;
• forming a first spacer insulating layer on the gate group;
• forming a spacer mask pattern on the first spacer insulating layer, side surfaces of the gate group disposed between side surfaces of the spacer mask pattern;
• and
• etching the first spacer insulating layer using the spacer mask pattern as an etch mask.

A method of manufacturing a semiconductor device, comprising:

• preparing a substrate including a cell region and a peripheral region;
• forming a gate group including cell gate patterns and at least one selection gate pattern on the cell region of the substrate;
• forming a peripheral gate pattern on the peripheral region of the substrate;
• forming a first spacer insulating layer on the gate group and the peripheral gate pattern;
• forming a cell mask pattern on the gate group, a width of the cell mask pattern being wider than a width of the gate group;
• forming a peripheral mask pattern on the peripheral gate pattern, a width of the peripheral mask pattern being wider than a width of the peripheral gate pattern;
• forming a first group spacer covering the gate group and a first pattern spacer covering the peripheral gate pattern by etching the first spacer insulating layer using the cell mask pattern and the peripheral mask pattern.

A method of manufacturing a semiconductor device, comprising:

• forming a gate group including a first selection line, a second selection line and a word lines between the first selection line and the second selection line;
• forming a first spacer insulating layer on the gate group;
• forming a mask pattern on the first spacer, the mask pattern including a first side surface disposed outside the first selection line of the gate group, and a second side surface disposed outside the second selection line of the gate group;
• forming a first spacer covering a top surface and side surfaces of the gate group by etching the first spacer insulating layer using the mask pattern,
• wherein the first spacer including a first discontinuity point disposed near the first selection line and a second discontinuity point disposed near the second selection line.