Semiconductor device manufacturing method
AssigneeFujitsu Semiconductor Limited
InventorsMasaki OKUNO, Hajime YAMAMOTO
Life of this patent
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Abstract
A semiconductor manufacturing method includes exposing on a photoresist film a first partial pattern of a contact hole, overlapping a part of a gate interconnection in alignment with an alignment mark formed simultaneously with forming the gate interconnection, exposing on the photoresist film a second partial pattern, overlapping a part of an active region in alignment with an alignment mark formed simultaneously with forming the active region, developing the photoresist film to form an opening at the portion where the first partial pattern and the second partial pattern have been exposed, and etching an insulation film to form a contact hole down to the gate interconnection and the source/drain diffused layer.
Claims4
A semiconductor device manufacturing method comprising:
- forming a device isolation region for defining a plurality of active regions in a semiconductor substrate and forming a first alignment mark in the semiconductor substrate;
- forming a first gate interconnection which is formed, crossing over one of said plurality of active regions and which is linear and includes the gate electrode of a first transistor, and a second gate interconnection which is formed, crossing over the other of said plurality of active regions and which is linear and in parallel with the first gate interconnection over the semiconductor substrate with a gate insulation film formed therebetween, and forming a second alignment mark over the semiconductor substrate;
- forming source/drain diffused layers respectively in the active regions on both sides of the gate electrodes;
- forming the first insulation film over the semiconductor substrate, the first gate interconnection and the second gate interconnection;
- forming over the first insulation film the second insulation film which is different from the first insulation film in the etching characteristics;
- forming the first photoresist film over the second insulation film;
- making alignment by using the second alignment mark and exposing on the first photoresist film a first partial pattern for a first contact hole in the first insulation film, overlapping at least a part of the first gate interconnection;
- developing the first photoresist film to form a first opening in the first photoresist film at the portion where the first partial pattern has been exposed;
- etching the second insulation film by using as the mask the first photoresist film with the first opening formed in;
- forming a second photoresist film over the second insulation film;
- making alignment by using the first alignment mark to expose on the second photoresist film a second partial pattern for forming the first contact hole in the first insulation film, overlapping at least a part of the source/drain diffused layer of the second transistor;
- developing the second photoresist film to form a second opening in the second photoresist film at the portion where the second partial pattern has been exposed;
- etching the second insulation film by using as the mask the second photoresist film with the second opening formed in;
- etching the first insulation film with the second insulation film as the mask to form in the first insulation film the first contact hole down to the first gate interconnection and the source/drain diffused layer of the second transistor;
- and
- burying the first contact layer in the first contact hole.
Dependencies are inferred from the claim text.