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US 2014/0179070 A1Published application
Anti-Fuses on Semiconductor Fins
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorHsiao-Lan Yang
Life of this patent
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Abstract
A device includes a substrate, isolation regions at a surface of the substrate, and a semiconductor region over a top surface of the isolation regions. A conductive feature is disposed over the top surface of the isolation regions, wherein the conductive feature is adjacent to the semiconductor region. A dielectric material is disposed between the conductive feature and the semiconductor region. The dielectric material, the conductive feature, and the semiconductor region form an anti-fuse.
Claims19
A method comprising:
- performing an epitaxy to form an epitaxy region over a top surface of a Shallow Trench Isolation (STI) region, wherein the STI region is at a surface of a substrate;
- forming a silicide region over and contacting the epitaxy region;
- forming a conductive region adjacent to the silicide region and over the STI region;
- filling a dielectric material between the conductive region and a combined region of the silicide region and the epitaxy region, wherein the conductive region, the combined region, and the dielectric material form an anti-fuse;
- and
- connecting a power source to the silicide region and the conductive region, wherein the power source is configured to apply a programming voltage high enough to program the anti-fuse.
3 more elements
A method comprising:
- epitaxially growing a first epitaxy region and a second epitaxy region, wherein corners of the epitaxy region and a second epitaxy region face each other;
- forming a first silicide region over and contacting the first epitaxy region;
- forming a second silicide region over and contacting the second epitaxy region;
- filling a dielectric material between first silicide region and the second silicide region, wherein the first silicide region, the second silicide region, and a portion of the dielectric material in between form an anti-fuse;
- and
- connecting a power source to the first silicide region and the second silicide region, wherein the power source is configured to apply a programming voltage high enough to program the anti-fuse.
3 more elements
A method comprising:
- applying a programming voltage to program an anti-fuse, wherein the anti-fuse comprises:
- a first semiconductor fin over top surfaces of Shallow Trench Isolation (STI) regions, wherein the first semiconductor fin comprise facets;
- a first silicide region contacting the first semiconductor fin;
- a conductive feature adjacent to the first semiconductor fin;
- and
- a dielectric material between the first semiconductor fin and the conductive feature, wherein the dielectric material, the first silicide region, and the first silicide region form the anti-fuse, and wherein during the applying the programming voltage, a portion of the dielectric material between the first semiconductor fin and the first silicide region are broken down.
3 more elements
Dependencies are inferred from the claim text.