US 2014/0177771 A1Published application

Clock data recovery circuit, data reception apparatus, and data transmission and reception system

AssigneeSony Corporation

InventorsKenichi Maruko, Yosuke Ueno

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Abstract

A clock data recovery circuit includes: an oscillator that outputs a clock signal; a phase comparator that outputs a signal corresponding to a phase difference between an input reception data signal and the clock signal; a divider that outputs a feedback clock signal; a first variable delay circuit that outputs a delay data signal; a second variable delay circuit that outputs a delay feedback clock signal; a frequency phase comparator that outputs a signal corresponding to a frequency difference and a phase difference between the delay data signal and the delay feedback clock signal; a lock detector that outputs a determination signal indicating whether or not the frequency difference and the phase difference are within a predetermined range; and a multiplexer that receives the determination signal and select a signal of the phase comparator and a signal of the frequency phase comparator.

Claims12

Dependent claims

A clock data recovery circuit, comprising:

an oscillator configured to output a clock signal;
a phase comparator configured to output a signal corresponding to a phase difference between an input reception data signal and the clock signal;
a divider configured to output a feedback clock signal obtained by dividing the clock signal by a predetermined division ratio;
a first variable delay circuit configured to output a delay data signal obtained by providing a first predetermined delay time to the reception data signal;
a second variable delay circuit configured to output a delay feedback clock signal obtained by providing a second predetermined delay time to the feedback clock signal;
a frequency phase comparator configured to output a signal corresponding to a frequency difference and a phase difference between the delay data signal and the delay feedback clock signal;
a lock detector configured to output a determination signal indicating whether or not the frequency difference and the phase difference between the delay data signal and the delay feedback clock signal are within a predetermined range;
and
a multiplexer configured to receive the determination signal and select a signal of the phase comparator and a signal of the frequency phase comparator.

6 more elements

A data reception apparatus, comprising:

a clock data recovery circuit including
an oscillator configured to output a clock signal,
a phase comparator configured to output a signal corresponding to a phase difference between an input reception data signal and the clock signal,
a divider configured to output a feedback clock signal obtained by dividing the clock signal by a predetermined division ratio,
a first variable delay circuit configured to output a delay data signal obtained by providing the first predetermined delay time to the reception data signal,
a second variable delay circuit configured to output a delay feedback clock signal obtained by providing the second predetermined delay time to the feedback clock signal,
a frequency phase comparator configured to output a signal corresponding to a frequency difference and a phase difference between the delay data signal and the delay feedback clock signal,
a lock detector configured to output a determination signal indicating whether or not the frequency difference and the phase difference between the delay data signal and the delay feedback clock signal are within a predetermined range, and
a multiplexer configured to receive the determination signal and select a signal of the phase comparator and a signal of the frequency phase comparator;
a deserializer configured to perform serial-parallel conversion on the reception data signal using the clock signal;
and
a decoder configured to decode modulated data output by the deserializer using the clock signal.

9 more elements

A data transmission and reception system, comprising:

a data transmission apparatus configured to transmit serial data;
and
a data reception apparatus including
a clock data recovery circuit including
an oscillator configured to output a clock signal,
a phase comparator configured to output a signal corresponding to a phase difference between an input reception data signal and the clock signal,
a divider configured to output a feedback clock signal obtained by dividing the clock signal by a predetermined division ratio,
a first variable delay circuit configured to output a delay data signal obtained by providing a first predetermined delay time to the reception data signal,
a second variable delay circuit configured to output a delay feedback clock signal obtained by providing a second predetermined delay time to the feedback clock signal,
a frequency phase comparator configured to output a signal corresponding to a frequency difference and a phase difference between the delay data signal and the delay feedback clock signal,
a lock detector configured to output a determination signal indicating whether or not the frequency difference and the phase difference between the delay data signal and the delay feedback clock signal are within a predetermined range, and
a multiplexer configured to receive the determination signal and select a signal of the phase comparator and a signal of the frequency phase comparator the determination signal,
a deserializer configured to perform serial-parallel conversion on the reception data signal using the clock signal, and
a decoder configured to decode modulated data output by the deserializer using the clock signal.

11 more elements

Dependencies are inferred from the claim text.