Synchronous transfer of streaming data in a distributed antenna system
AssigneeAndrew Corporation
InventorsDonald Robert McAllister, Christopher Goodman Ranson, Fred William Phillips
Life of this patent
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Abstract
Embodiments of the invention provide a method, distributed antenna system, and components that generate a jitter reduced clock signal from a binary encoded data stream transmitted over a communication medium. The method includes receiving a modulated signal that includes the binary encoded data stream and generating a recovered clock signal that is phase locked to the binary encoded data stream. The method further comprises generating a stable recovered clock signal by filtering the recovered clock signal to remove jitter, while allowing the clock signal to track long-term drift.
Claims21
A method of generating a jitter reduced clock signal from signal transmitted over a communication medium, the method comprising:
- receiving, with high speed data interface circuitry, a modulated signal that includes a binary encoded data stream;
- generating a recovered clock signal that is phase locked to the binary encoded data stream with circuitry having a filter with a bandwidth that does not substantially block the long-term drift in the modulated signal;
- generating a stable recovered clock signal by filtering the recovered clock signal using a filtering circuit having a bandwidth narrower than the bandwidth of the circuitry that is used for generating the recovered clock signal in order to remove jitter while allowing the stable recovered clock signal to track drift of the binary encoded data stream.
A distributed antenna system, comprising:
- a master unit that clocks a binary encoded data stream onto high speed data interface circuitry using a modulated signal based upon an output of a reference oscillator;
- at least one remote unit that receives the modulated signal and binary encoded data stream from the master unit, the at least one remote unit including:
- a clock recovery circuit that is configured to generate a recovered clock signal that is phase-locked to the binary encoded data stream and that includes a filter configured with a bandwidth that does not substantially block the long-term drift in the modulated signal;
- a filtering circuit having a bandwidth narrower than the bandwidth of the filter of the clock recovery circuit and that is configured to filter the recovered clock signal in order to remove jitter while allowing the recovered clock signal to track long-term drift of the binary encoded data stream for generating a stable recovered clock signal.
A master unit for a distributed antenna system, comprising:
- high speed data interface circuitry for exchange of data with at least one remote unit;
- first RF transceiver circuitry for communicating with at least a first base transceiver system;
- second RF transceiver circuitry for communicating with at least a second base transceiver system;
- auxiliary interface circuitry for communicating with other services;
- a processing unit that multiplexes data from the auxiliary interface, the first RF transceiver circuitry, and the second RF transceiver circuitry and routes the multiplexed data to a PHY for transmission via the high speed data interface circuitry, and that de-multiplexes data from the high speed data interface circuitry and routes the de-multiplexed data to at least one of the auxiliary interface, the first RF transceiver circuitry, and the second RF transceiver circuitry;
- and
- a reference oscillator that is used to multiplex and/or de-multiplex the data to and/or from the high speed data interface.
A method of generating a jitter reduced clock signal from an encoded data stream, the method comprising:
- generating a recovered clock signal that is phase locked to the binary encoded data stream with circuitry having a filter with a bandwidth that does not substantially block the long-term drift in the modulated signal;
- clocking data from the encoded data stream into a processing unit based on the recovered clock signal;
- detecting a periodic signal component, other than the bit rate, of the encoded data stream with the processing unit;
- generating a reference clock signal based on the detected periodic signal component.
Dependencies are inferred from the claim text.