US 2014/0177699 A1Published application

Equalizer and semiconductor device

AssigneeRenesas Electronics Corporation

InventorsKenzo TAN, Masahiro TAKEUCHI

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Abstract

An equalizer includes a first discrimination circuit to receive an input signal corresponding to a signal output from a transmit-side equalizer to binarize the input signal by a first threshold value in unit time, a second discrimination circuit to binarize the input signal by a second threshold value in unit time, a first delay circuit to delay an output signal of the first discrimination circuit and that includes N-number (N>=2) of stages of unit delay circuits connected in cascade and operating in unit time, a second delay circuit to receives an output signal of the second discrimination circuit and that includes not less than an (N+1)-number of stages of unit delay circuits connected in cascade and operating in unit time, and a control unit that receives an output of the first delay circuit, and a second output signal output from the second delay circuit.

Claims15

Dependent claims

An equalizer comprising:

first and second discrimination circuits configured to receive in common an input signal corresponding to a signal output from a transmit-side equalizer,
the first discrimination circuit configured to perform binarization of the input signal using a first threshold value to produce a first binary signal, in unit time,
the second discrimination circuit configured to perform binarization of the input signal using a second threshold value to produce a second binary signal, in the unit time;
a first delay circuit configured to receive the first binary signal output from the first discrimination circuit to delay the first binary signal, the first delay circuit comprising an N-number of stages of unit delay circuits connected in cascade, N being an greater than or equal to 2, each of the unit delay circuits configured to operate in the unit time;
and
a control unit configured to receive, as respective first and second output signals, an output signal output from the first delay circuit and the second binary signal output from the second discrimination circuit to perform control so that a coefficient of a temporally most precedent precursor in the transmit-side equalizer is not increased, when the first output signal and the second output signal have polarities not coincident with each other.

3 more elements

An equalizer comprising:

first and second discrimination circuits configured to receive in common an input signal corresponding to a signal output from a transmit-side equalizer,
the first discrimination circuit configured to perform binarization of the input signal using a first threshold value to produce a first binary signal, in unit time,
the second discrimination circuit configured to perform binarization of the input signal using a second threshold value to produce a second binary signal, in the unit time;
a first delay circuit configured to receive the first binary signal output from the first discrimination circuit to delay the first binary signal, the first delay circuit comprising an N-number of stages of unit delay circuits connected in cascade, N being an greater than or equal to 2, each of the unit delay circuits configured to operate in the unit time;
a second delay circuit configured to receive the second binary signal output from the second discrimination circuit to delay the second binary signal, the second delay circuit comprising not less than an (N+1)-number of stages of unit delay circuits connected in cascade, each of the unit delay circuits configured to operate in the unit time;
and
a control unit configured to receive, as respective first to third output signals, an output signal output from the first delay circuit, the second binary signal output from the second discrimination circuit, and an output signal output from a first stage unit delay circuit of the second delay circuit, respectively, the control unit performing control so that a coefficient of the temporally most precedent precursor in the transmit-side equalizer is
(a) increased,
(b) decreased or
(c) unchanged, respectively, depending on whether t1+t2·Z is
(a) greater than a second value,
(b) less than a third value, or
(c) not greater than the second value and not less than the third value, where, during a preset time period which is an integer number times of the unit time,
t1 is the number of times that polarities of the first and third signals are coincident with each other, less the number of times that the polarities of the first and third signals are not coincident with each other, and
t2 is the number of times that the polarities of the first and second signals are coincident with each other, less the number of times that the polarities of the first and second signals are not coincident with each other, and
Z is a positive real number.

13 more elements

Dependencies are inferred from the claim text.