Decision feedback equalizer using current mode processing with cmos compatible output level
AssigneeNVIDIA Corporation
InventorsNam D. Nguyen, Ismail H. Ozguc
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Abstract
A decision feedback equalizer system is disclosed. The decision feedback equalizer system includes a current summer core that in current mode, removes inter-symbol interference from a signal, and, a CMOS latch component, that is coupled to the current summer core, that receives a current mode signal and outputs a CMOS compatible signal. The components of the decision feedback equalizer system are controlled by a single clock.
Claims20
A decision feedback equalizer system, said system comprising:
- a current summer core, that in current mode, is operable to remove inter-symbol interference from a signal;
- and
- a CMOS latch component coupled to said current summer core, that is operable to receive a current mode signal and operable to output a CMOS compatible signal, wherein components of said decision feedback equalizer system are controlled by a single clock.
The system of claim 8 wherein said plurality of switches comprise a common mode sensor.
An equalizer system, said system comprising:
- a degeneration amplifier;
- a plurality of current summer core pairs, coupled to said degeneration amplifier, that are a part of a plurality of systems for processing a signal received from said degeneration amplifier, wherein at least one of said plurality of systems comprise:
- a current summer core, that in current mode, is operable to remove inter-symbol interference from a signal;
- and
- a CMOS latch component coupled to said current summer core, that is operable to receive a current mode signal and outputs a CMOS compatible signal, wherein components of said decision feedback equalizer system are controlled by a single clock.
A method of operating a decision feedback equalizer system, said method comprising:
- receiving a bit of data into a current summer core of said decision feedback equalizer system;
- receiving into said current summer core a determined measure of inter-symbol interference;
- subtracting said determined measure of inter-symbol interference from said bit of data to generate an equalized data bit;
- providing said equalized data bit to a CMOS latch that is directly coupled to said current summer core;
- and
- providing access to said equalized data bit at a CMOS compatible level.
Dependencies are inferred from the claim text.