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US 2014/0177470 A1Published application
Memory Sharing in a Network Device
AssigneeMarvell World Trade Ltd.
InventorsAmir Roitshtein, Gil Levy, Gideon Paul
Life of this patent
Estimating the term…
Abstract
A network device includes processor devices configured to perform packet processing functions, and a shared memory system including multiple memory blocks. A memory connectivity network couples the processor devices to the shared memory system. A configuration unit configures the memory connectivity network so that processor devices are provided access to respective sets of memory blocks.
Claims22
A network device, comprising:
- a plurality of processor devices configured to perform packet processing functions;
- a shared memory system including a plurality of memory blocks, each memory block corresponding to a respective portion of the shared memory system, and each memory block having a respective size less than a total size of the shared memory system;
- and
- a memory connectivity network to couple the plurality of processor devices to the shared memory system;
- and
- a configuration unit to configure the memory connectivity network so that processor devices among the plurality of processor devices are provided access to respective sets of memory blocks among the plurality of memory blocks.
3 more elements
A method, comprising:
- determining memory requirements of a plurality of processor devices of a network device, the plurality of processors devices for performing packet processing functions on packets received from a network;
- assigning, in the network device, memory blocks of a shared memory system to processor devices among the plurality of processor devices based on the determined memory requirements of respective processor devices, each memory block corresponding to a respective portion of the shared memory system, and each memory block having a respective size less than a total size of the shared memory system;
- and
- configuring, in the network device, a memory connectivity network that couples the plurality of processor devices to the shared memory system so that processor devices among the plurality of processor devices are provided access to respective assigned sets of memory blocks among the plurality of memory blocks.
1 more element
Dependencies are inferred from the claim text.